Digital clock signals play important roles in information handling systems (IHSs) such as desktop, laptop, notebook, personal digital assistant (PDA), server, mainframe, minicomputer and communication systems, and other systems that employ digital electronics. For example, a microprocessor in an IHS employs a clock signal as a time base or reference. In actual practice, IHSs typically employ multiple clock signals that all relate to a common system clock signal, namely a master clock signal.
A practical IHS may include hardware that generates multiple clock signals from a common system clock or master clock signal. The master clock signal acts as the primary timing reference for the IHS. The other clock signals in the IHS relate to the master clock signal in timing, frequency and pulse width. Moreover, the rising and falling edges of the other clock signals may relate to the rising and falling edges of the master clock signal to provide the proper timing of operations within the IHS. In the simplest case, the other clock signals relate to the master clock signal by an integer multiple. For example, the other clock signals may exhibit a frequency twice or three times that of the master clock signal.
It is also possible for a clock circuit to divide the master clock signal by an integer divisor to produce a clock signal exhibiting a lower frequency than the master clock signal. For example, a divide by 2 clock circuit divides the master clock signal by 2 to generate a clock signal that exhibits a frequency ½ the system clock frequency. Typically, the resultant clock signal exhibits a 50/50 duty cycle. In other words, one half cycle of the clock signal exhibits a logic high while the next half cycle of the clock signal exhibits a logic low. Divide by 2 clock circuits with 50/50 duty cycles are common. Clock circuits with 50/50 duty cycles and employing integer divisors other than 2, for example divisors of 3, 4, or 5, are also common.
A less common clock circuit is the “divide by X.5” clock circuit in which clock circuitry divides a master clock signal or system clock signal by a divisor, X.5, wherein X describes an integer greater than or equal to 2. For example, clock circuits may employ divisors of 2.5, 3.5, 4.5, etc. to divide the master clock signal to produce a resultant divided down clock signal. A divide by X.5 clock circuit is useful in complex integrated circuits that perform memory addressing, memory data management and a wide variety of other integrated circuit functions as well. Divide by X.5 clock circuits are known that exhibit duty cycles other than 50/50. However, some applications require 50-50 duty cycle clock signals. For example, double data rate memory systems require 50-50 duty cycle clock signals because these systems launch and capture data on both the rising and falling edges of a clock signal. Timing requirements in many high-speed applications mandate a clock signal that maintains an ideal 50-50 duty cycle.
What is needed is a method and apparatus that divides a clock signal by a non-integer divisor to provide an output signal exhibiting a 50/50 duty cycle.